1. Field of the Invention
The present invention relates to a semiconductor integrated circuit configured to minimize the adverse effects of power noise caused by an overcurrent.
2. Description of the Related Art
An integrated circuit with either a single or a plurality of functions, in which a great number of semiconductor elements are integrated into a single chip, is commonly known as an IC. The IC chip is housed in a cavity which protects it from the surrounding atmosphere. The semiconductor chip contains many pad electrodes for signal transfers and power supplies.
FIG. 1 illustrates a block diagram of a typical circuit contained in a memory IC chip. External address signals input to the memory circuit first reach pad electrodes 11, 11 of the memory circuit. The address signals are then inputted to an address buffer circuit 12 and to an address decoder circuit 13. By decode signals outputted from the address decoder circuit 13, data of a plurality of bits are read out of a memory 14, and amplified by a sense amplifier circuit 15. The amplified data signals are applied to an output buffer circuit 17. The data signals loaded in the output buffer circuit 17 are output through pad electrodes 18, 18.
To operate the memory IC chip, external power and ground voltages must be supplied. A power voltage Vcc is applied to a power pad electrode 19. Two ground voltages Vss1 and Vss2 are respectively applied to pads 20 and 21 exclusively used for ground voltage application. Pad electrodes 18, 18 for data outputting contain parasitic capacitances that are treated as a load capacitor 24.
The power voltage Vcc applied to the pad electrode 19 is supplied to an internal circuit 22 and a peripheral circuit 23. The internal circuit 22 is made up of the address buffer 12, address decoder 13, memory 14 and sense amplifier circuit 15. The peripheral circuit 23 is made up of the output circuit 16 and the output buffer circuit 17. Of the two types of ground voltages Vss1 and Vss2, the ground voltage Vss1is applied to the internal circuit 22. The ground voltage Vss2 is applied to the peripheral circuit 23. The rationale for applying two different ground voltages to those circuits is described below.
There are many types of memory ICs. Static RAMs and ROMs, as typical memory ICs, generally use a multi-bit approach, for example, 8 bits or 16 bits, for the output data. The load capacitor 24, a parasite on the pad electrodes for outputting the multibit data is usually about 100 pF. In the memory handling the multibit data, it is required to simultaneously charge and discharge a plurality of load capacitors. At this time, large currents caused by the charge-discharge flow through the power interconnections in the chip. Particularly for ground voltage interconnections of long length and high line resistance and inductance, the flow of a large current therethrough results in a great variation of the ground voltages. Taking the above fact into account, the ground voltage Vss1 is applied to the internal circuit 22, and another ground voltage Vss2 is applied to the peripheral circuit 23 containing the output buffer through which a large current possibly flows. With such ground voltage supplies, even when noise is generated in the ground voltage Vss2, the ground voltage Vss1 is isolated from that noise. In other memory circuits, the ground potential Vss1 is applied to the output circuit 16 as well as the internal circuit 22, and the ground voltage Vss2 is applied to only the output buffer 17.
The IC package is provided with a lead frame containing inner leads and outer leads integral with the inner leads, in addition to the semiconductor chip. Before packaging, the tips or ends of the inner leads are electrically coupled with the pad electrodes by means of metal wires of Au or Al, for example, called bonding wires. After the inner leads and pad electrodes are coupled by the bonding wires, the inner leads, together with the semiconductor chip, are hermetically encapsulated into a cavity, while the outer leads are left outside the cavity. The outer leads are then bent and cut as required, and are used as the external terminals of the DIP type.
FIG. 2 shows the interior of a conventional 28-pin IC package that houses a memory IC chip. A memory IC chip 31 is provided with many pad electrodes including a pad electrode 19 for the power voltage Vcc, and pad electrodes 20 and 21 for the ground voltages Vss1 and Vss2. Reference numerals 32 designate inner leads on a lead frame; reference numerals 33 designate bonding wires; and reference numeral 34 designates a cavity. In the illustration, pad electrodes other than those for power voltages and the outer leads on the lead frame are omitted for simplicity.
As illustrated, the ground voltage for use in the circuits handling large currents such as the output buffer is different from the ground voltage for the remaining circuits. The lead frame, however, is common for both the inner and output leads.
In recent high speed memory devices with reduced access times, a variation of the ground voltage which is due to the inductance components of the lead frame for the ground voltage supply, becomes significant. Let us obtain an inductance of the inner lead 32 on the lead frame for ground voltage supply in the structure as shown in FIG. 2 A self-inductance of the inner lead may be approximated by: ##EQU1## where l: Length of the inner lead,
w: Width of the same, PA1 t: Thickness of the same.
We have 12.8 nH, when the following specific values are applied to the above formula: l=1.5 cm, w=0.05 cm, and t=0.02 cm.
Let us obtain a discharge current of the output buffer in the memory device of FIG. 1. A portion including mainly the output buffer circuit 17 may equivalently be depicted as shown in FIG. 3. In FIG. 3, C represents the load capacitance; Q represents an n-channel output transistor in the output buffer circuit 17 for discharging the load capacitor C; L represents a self-inductance component existing in the inner lead on the lead frame for the ground voltage supply. The equivalent circuit of FIG. 3 represents the memory device when the discharge of the load capacitor C progresses. In this operation mode, a p-channel output transistor for charging purposes which is connected to a power voltage Vcc in the output buffer is in an off state. Therefore, it is omitted in the illustration. When the memory device is an 8-bit type, the capacitance of the load capacitor C is 800 pF because a capacitance for one bit is 100 pF, and hence 100 pF.times.8=800 pF. Generally, the channel width W and the channel length L of one output transistor are: W=300 .mu.m and L=2.2 .mu.m. The equivalent channel width W and channel length L of the output transistor Q for 8 bits are 2400 .mu.m and 2.2 .mu.m.
In the above equivalent circuit, a variation of a discharge current I.sub.s was simulated by a computer under conditions that the load capacitor C is charged at 5 V by a signal D.sub.in, and signal D.sub.in is applied to the gate of the output transistor Q, as shown in FIG. 4. The variation of the discharge current I.sub.s simulated was shown in FIG. 5. Noise appearing in the ground voltage Vss2 is proportional to a rate of change of the discharge current I.sub.s with respect to time "t", viz., dI.sub.s /dt. A maximum changing rate of discharge current, i.e., dI.sub.s /dt (max), is defined by an inclination of a slanted line A, and approximately 78.times.106 (A/sec). Accordingly, a maximum ground voltage Vss2 (max) at the pad electrode 21 when the load capacitor is discharged is EQU Vss2(max)=L.times.dI.sub.s /dt(max) (2)
Substituting the above specific figures, L=12.8 nH and dI.sub.s /dt(max)=78.times.10.sup.6 A/sec, into the relation (2), we have Vss2(max)=1 V. This shows that in the memory IC shown in FIG. 2, a potential at the pad electrode 21 which should be at 0 V, rises up to a maximum of 1 V. This great voltage variation at the electrode 21 transfers to the pad electrode 20. Because of this, the internal circuit of the conventional memory IC tends to operate improperly.